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Jiang Long
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Smart simulation using collaborative formal and simulation engines
PH Ho, T Shiple, K Harer, J Kukula, R Damiano, V Bertacco, J Taylor, ...
Ieee/acm international conference on computer aided design. iccad-2000. ieee …, 2000
1752000
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
D Wang, PH Jiang, J Kukula, Y Zhu, T Ma, R Damiano
Proceedings of the 38th annual Design Automation Conference, 35-40, 2001
1062001
Synthesizing SVA local variables for formal verification
J Long, A Seawright
Proceedings of the 44th annual Design Automation Conference, 75-80, 2007
252007
Enhancing abc for ltl stabilization verification of systemverilog/vhdl models
J Long, S Ray, B Sterin, A Mishchenko, R Brayton
Ganesh Gopalakrishnan University of Utah USA 38, 2011
122011
LEC: Learning-Driven Data-path Equivalence Checking
J Long, RK Brayton, M Case
Program Proceedings, 9, 2013
52013
SVA local variable coding guidelines for efficient use
J Long, A Seawright, H Foster
Proceedings of DVCon, 2007
52007
Multi-clock SVA synthesis without re-writing
J Long, A Seawright, P Kavalipati
2009 Asia and South Pacific Design Automation Conference, 648-653, 2009
32009
Reasoning about High-Level Constructs in Hardware/Software Formal Verification
J Long
University of California, Berkeley, 2017
12017
A Simple C to Verilog Compilation Procedure for Hardware/Software Verification
J Long, R Brayton
1
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