| ERSA: Error resilient system architecture for probabilistic applications L Leem, H Cho, J Bau, QA Jacobson, S Mitra 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 309 | 2010 |
| Quantitative evaluation of soft error injection techniques for robust system design H Cho, S Mirkhani, CY Cher, JA Abraham, S Mitra Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013 | 300 | 2013 |
| ERSA: Error resilient system architecture for probabilistic applications H Cho, L Leem, S Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 148 | 2012 |
| CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining hardware and software techniques to tolerate soft errors in processor cores E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 100 | 2016 |
| ASIC-resistance of multi-hash proof-of-work mechanisms for blockchain consensus protocols H Cho IEEE Access 6, 66210-66222, 2018 | 93 | 2018 |
| Gallager B decoder on noisy hardware SMST Yazdi, H Cho, L Dolecek IEEE Transactions on Communications 61 (5), 1660-1673, 2013 | 88 | 2013 |
| Dynamic data scratchpad memory management for a memory subsystem with an MMU H Cho, B Egger, J Lee, H Shin Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages …, 2007 | 70 | 2007 |
| Fa3c: Fpga-accelerated deep reinforcement learning H Cho, P Oh, J Park, W Jung, J Lee Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 69 | 2019 |
| The resilience wall: Cross-layer solution strategies S Mitra, P Bose, E Cheng, CY Cher, H Cho, R Joshi, YM Kim, CR Lefurgy, ... Proceedings of Technical Program-2014 International Symposium on VLSI …, 2014 | 50 | 2014 |
| Impact of microarchitectural differences of RISC-V processor cores on soft error effects H Cho IEEE Access 6, 41302-41313, 2018 | 32 | 2018 |
| Understanding soft errors in uncore components H Cho, CY Cher, T Shepherd, S Mitra Proceedings of the 52Nd Annual Design Automation Conference, 1-6, 2015 | 29 | 2015 |
| Tolerating soft errors in processor cores using clear (cross-layer exploration for architecting resilience) E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 28 | 2017 |
| System-level effects of soft errors in uncore components H Cho, E Cheng, T Shepherd, CY Cher, S Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 23 | 2017 |
| Cross-layer error resilience for robust systems L Leem, H Cho, HH Lee, YM Kim, Y Li, S Mitra 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 177-180, 2010 | 23 | 2010 |
| Robust system design S Mitra, H Cho, T Hong, YM Kim, HHK Lee, L Leem, Y Li, D Lin, ... IPSJ Transactions on System and LSI Design Methodology 4, 2-30, 2011 | 19 | 2011 |
| Rethinking error injection for effective resilience S Mirkhani, H Cho, S Mitra, JA Abraham 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 390-393, 2014 | 17 | 2014 |
| FARNN: FPGA-GPU hybrid acceleration platform for recurrent neural networks H Cho, J Lee, J Lee IEEE Transactions on Parallel and Distributed Systems 33 (7), 1725-1738, 2021 | 13 | 2021 |
| Cross-layer resilience: Challenges, insights, and the road ahead E Cheng, J Abraham, P Bose, A Buyuktosunoglu, D Chen, H Cho, Y Li, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 12 | 2019 |
| Correction to “ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols” H Cho IEEE Access 7, 25086-25086, 2019 | 12 | 2019 |
| Probabilistic analysis of Gallager B faulty decoder SMST Yazdi, H Cho, Y Sun, S Mitra, L Dolecek 2012 IEEE International Conference on Communications (ICC), 7019-7023, 2012 | 12 | 2012 |
