| Elective surgery cancellations due to the COVID-19 pandemic: global predictive modelling to inform surgical recovery plans Journal of British Surgery 107 (11), 1440-1449, 2020 | 1249 | 2020 |
| Performance of processor-memory interconnections for multiprocessors Patel IEEE Transactions on computers 100 (10), 771-780, 1981 | 1032 | 1981 |
| HITEC: A test generation package for sequential circuits T Niermann, JH Patel Proceedings of the European Conference on Design Automation., 214-218, 1991 | 882 | 1991 |
| A low-overhead coherence solution for multiprocessors with private cache memories MS Papamarcos, JH Patel Proceedings of the 11th annual international symposium on Computer …, 1984 | 818 | 1984 |
| Test set compaction algorithms for combinational circuits I Hamzaoglu, JH Patel Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 608 | 1998 |
| Stride directed prefetching in scalar processors JWC Fu, JH Patel, BL Janssens ACM SIGMICRO Newsletter 23 (1-2), 102-110, 1992 | 475 | 1992 |
| Reducing test application time for full scan embedded cores I Hamzaoglu, JH Patel Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999 | 452 | 1999 |
| Concurrent error detection in ALU's by recomputing with shifted operands Patel, Fung IEEE Transactions on computers 100 (7), 589-595, 1982 | 432 | 1982 |
| PROOFS: A fast, memory-efficient sequential circuit fault simulator TM Niermann, WT Cheng, JH Patel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992 | 404 | 1992 |
| Reliability of scrubbing recovery-techniques for memory systems AM Saleh, JJ Serrano, JH Patel IEEE transactions on reliability 39 (1), 114-122, 1990 | 283 | 1990 |
| Sequential circuit test generation in a genetic algorithm framework EM Rudnick, JH Patel, GS Greenstein, TM Niermann Proceedings of the 31st annual Design Automation Conference, 698-704, 1994 | 254 | 1994 |
| Accurate low-cost methods for performance evaluation of cache memory systems S Laha, JH Patel, RK Iyer IEEE Transactions on computers 37 (11), 1325-1336, 1988 | 236 | 1988 |
| Sequential circuit test generation using dynamic state traversal MS Hsiao, EM Rudnick, JH Patel Proceedings European Design and Test Conference. ED & TC 97, 22-28, 1997 | 212 | 1997 |
| Data prefetching in multiprocessor vector cache memories JWC Fu, JH Patel ACM SIGARCH Computer Architecture News 19 (3), 54-63, 1991 | 208 | 1991 |
| New techniques for deterministic test pattern generation I Hamzaoglu, JH Patel Journal of Electronic Testing 15, 63-73, 1999 | 198 | 1999 |
| An optimization based approach to the partial scan design problem V Chickermane, JH Patel Proceedings. International Test Conference 1990, 377-386, 1990 | 188 | 1990 |
| Processor-memory interconnections for multiprocessors JH Patel Proceedings of the 6th Annual Symposium on Computer Architecture, 168-177, 1979 | 183 | 1979 |
| A case study on the implementation of the Illinois scan architecture FF Hsu, KM Butler, JH Patel Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 538-547, 2001 | 171 | 2001 |
| A gate-level simulation environment for alpha-particle-induced transient faults H Cha, EM Rudnick, JH Patel, RK Iyer, GS Choi IEEE Transactions on Computers 45 (11), 1248-1256, 1996 | 171 | 1996 |
| A logic-level model for/spl alpha/-particle hits in CMOS circuits H Cha, JH Patel Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 …, 1993 | 155 | 1993 |
Michael HsiaoProfessor, Virginia Tech, IEEE FellowBestätigte E-Mail-Adresse bei vt.edu
