| Analog layout generator for CMOS circuits E Yilmaz, GÜ Dundar IEEE Transactions on computer-aided design of integrated circuits and …, 2008 | 88 | 2008 |
| An industrial case study of analog fault modeling E Yilmaz, A Meixner, S Ozev 29th VLSI test symposium, 178-183, 2011 | 38 | 2011 |
| Fault analysis and simulation of large scale industrial mixed-signal circuits E Yilmaz, G Shofner, LR Winemberg, S Ozev 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 565-570, 2013 | 35 | 2013 |
| Adaptive test flow for mixed-signal/RF circuits using learned information from device under test E Yilmaz, S Ozev, KM Butler 2010 IEEE International Test Conference, 1-10, 2010 | 35 | 2010 |
| Adaptive multidimensional outlier analysis for analog and mixed signal circuits E Yilmaz, S Ozev, KM Butler 2011 IEEE International Test Conference, 1-8, 2011 | 34 | 2011 |
| Adaptive test elimination for analog/RF circuits E Yilmaz, S Ozev Proceedings of the 46th Annual Design Automation Conference, 720-725, 2009 | 32 | 2009 |
| Per-device adaptive test for analog/RF circuits using entropy-based process monitoring E Yilmaz, S Ozev, KM Butler IEEE transactions on very large scale integration (VLSI) systems 21 (6 …, 2012 | 28 | 2012 |
| Adaptive testing: Conquering process variations E Yilmaz, S Ozev, O Sinanoglu, P Maxwell 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 26* | 2012 |
| Built-in self-test for stability measurement of low dropout regulator JW Jeong, E Yilmaz, LR Winemberg, S Ozev 2017 IEEE International Test Conference (ITC), 1-9, 2017 | 17 | 2017 |
| Defect-based test optimization for analog/RF circuits for near-zero DPPM applications E Yilmaz, S Ozev 2009 IEEE International Conference on Computer Design, 313-318, 2009 | 17 | 2009 |
| Digital built-in self-test for phased locked loops to enable fault detection M Ince, E Yilmaz, W Fu, J Park, K Nagaraj, LR Winemberg, S Ozev 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 15 | 2019 |
| Dynamic test scheduling for analog circuits for improved test quality E Yilmaz, S Ozev 2008 IEEE International Conference on Computer Design, 227-233, 2008 | 15 | 2008 |
| Adaptive-learning-based importance sampling for analog circuit DPPM estimation E Yilmaz, S Ozev IEEE Design & Test 32 (1), 36-43, 2014 | 14 | 2014 |
| Functional path failure monitor X Wang, OG Shofner, DT Tran, LR Winemberg, E Yilmaz US Patent 9,222,971, 2015 | 12 | 2015 |
| Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information E Yilmaz, S Ozev 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 9 | 2012 |
| Test application for analog/rf circuits with low computational burden E Yilmaz, S Ozev IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 9 | 2012 |
| New layout generator for analog CMOS circuits E Yilmaz, G Dundar 2007 18th European Conference on Circuit Theory and Design, 36-39, 2007 | 9 | 2007 |
| Evaluation of loop transfer function based dynamic testing of LDOs M Ince, E Yilmaz, JW Jeong, LR Winemberg, S Ozev 2017 International Test Conference in Asia (ITC-Asia), 14-19, 2017 | 8 | 2017 |
| Fast and accurate DPPM computation using model based filtering E Yilmaz, S Ozev 2011 Sixteenth IEEE European Test Symposium, 165-170, 2011 | 8 | 2011 |
| Fault-based built-in self-test and evaluation of phase locked loops M Ince, E Yilmaz, W Fu, J Park, K Nagaraj, L Winemberg, S Ozev ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (3 …, 2021 | 7 | 2021 |
Sule OzevArizona State UniversityBestätigte E-Mail-Adresse bei asu.edu
