Sunil Shukla
Sunil Shukla
IBM Research
Bestätigte E-Mail-Adresse bei us.ibm.com - Startseite
Titel
Zitiert von
Zitiert von
Jahr
FPGA programming for the masses
DF Bacon, R Rabbah, S Shukla
Communications of the ACM 56 (4), 56-63, 2013
1852013
A scalable multi-TeraOPS deep learning processor core for AI trainina and inference
B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
2018 IEEE Symposium on VLSI Circuits, 35-36, 2018
952018
A compiler and runtime for heterogeneous computing
J Auerbach, DF Bacon, I Burcea, P Cheng, SJ Fink, R Rabbah, S Shukla
DAC Design Automation Conference 2012, 271-276, 2012
752012
Approximate computing: Challenges and opportunities
A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, J Oh, DA Prener, ...
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
732016
Single bit error correction implementation in CRC-16 on FPGA
S Shukla, NW Bergmann
Proceedings. 2004 IEEE International Conference on Field-Programmable …, 2004
712004
QUKU: a two-level reconfigurable architecture
S Shukla, NW Bergmann, J Becker
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006
552006
FPGA Programming for the Masses: The programmability of FPGAs must improve if they are to be part of mainstream computing.
D Bacon, R Rabbah, S Shukla
Queue 11 (2), 40-52, 2013
372013
QUKU: A FPGA based flexible coarse grain architecture design paradigm using process networks
S Shukla, NW Bergmann, J Becker
2007 IEEE International Parallel and Distributed Processing Symposium, 1-7, 2007
272007
QUKU: a dual-layer reconfigurable architecture
NW Bergmann, SK Shukla, J Becker
ACM Transactions on Embedded Computing Systems (TECS) 12 (1s), 1-26, 2013
242013
QUKU: A coarse grained paradigm for FPGAs
S Shukla, NW Bergmann, J Becker
Dagstuhl Seminar Proceedings, 2006
172006
QUKU: A fast run time reconfigurable platform for image edge detection
S Shukla, NW Bergmann, J Becker
International Workshop on Applied Reconfigurable Computing, 93-98, 2006
162006
And then there were none: A stall-free real-time garbage collector for reconfigurable hardware
DF Bacon, P Cheng, S Shukla
ACM SIGPLAN Notices 47 (6), 23-34, 2012
142012
A 3.0 tflops 0.62 v scalable processor core for high compute utilization ai training and inference
J Oh, SK Lee, M Kang, M Ziegler, J Silberman, A Agrawal, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
132020
A 7nm 4-Core AI Chip with 25.6 TFLOPS Hybrid FP8 Training, 102.4 TOPS INT4 Inference and Workload-Aware Throttling
A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021
112021
A scalable multi-TeraOPS core for AI training and inference
S Shukla, B Fleischer, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
IEEE Solid-State Circuits Letters 1 (12), 217-220, 2018
112018
Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits
CY Chen, K Gopalakrishnan, J Oh, SK Shukla, V Srinivasan
US Patent 10,120,685, 2018
102018
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware
DF Bacon, P Cheng, S Shukla
Communications of the ACM 56 (12), 101-109, 2013
92013
A fault modeling technique to test memory BIST algorithms
R Venkatesh, S Kumar, J Philip, S Shukla
Proceedings of the 2002 IEEE International Workshop on Memory Technology …, 2002
92002
Cycle-accurate replay and debugging of running FPGA systems
D Foisy, SK Shukla
US Patent 9,217,774, 2015
82015
Efficient AI system design with cross-layer approximate computing
S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ...
Proceedings of the IEEE 108 (12), 2232-2250, 2020
72020
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